When memory training begins on a platform with poorly aligned Control, Clock and Command/Address (CA) signals, even the most basic commands, such as Reset or entry into CA Training mode, might not register correctly in some of the DRAM devices. Current solutions demand very strict length matching and/or manual initial timing settings for all these signal types for each problematic platform. As a result, much time and efforts can be spent for just enabling the most basic training routines to run.